New Chip Design Boosts AI Efficiency at the Edge

Why this is here: E-ReCON’s adder tree reduces transistor count by approximately 37% compared to conventional designs, lowering power consumption.

Researchers at an unnamed institution in an unspecified location developed E-ReCON, a new computer chip for artificial intelligence tasks. The chip uses a “compute-in-memory” design.

This means it processes data directly within the memory itself, reducing energy use. E-ReCON is built with ReRAM, a type of memory that is compact and efficient.

The chip’s design includes a new adder tree. This reduces the number of transistors needed by roughly 37% and power consumption by about 28%.

Testing showed the chip achieves up to 419 TOPS/W, a measure of performance per watt. It maintained high accuracy—over 93%—on several image recognition tests.

The chip also works with “spiking neural networks,” a newer type of AI. It efficiently handles the unique demands of these networks.

While the results are promising, the chip was tested using a specific 65nm manufacturing process. Further work is needed to confirm performance with different processes and a wider range of AI models.